{"product_id":"logic-design-and-verification-using-systemverilog-revised-9781523364022","title":"Logic Design and Verification Using SystemVerilog (Revised)","description":"SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eAbout the Author\u003c\/b\u003e\u003cbr\u003eDonald Thomas is Professor Emeritus of Electrical and Computer Engineering at Carnegie Mellon University where he has taught logic design, RT-level design, design languages (Verilog and SystemVerilog), verification, and computer-aided design algorithms for the design of integrated circuits and systems.\u003cbr\u003e","brand":"Createspace Independent Publishing Platform","offers":[{"title":"Default Title","offer_id":50478318878994,"sku":"9781523364022","price":60.99,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0831\/4771\/8930\/files\/img_85161afb-13bd-4cd6-9cf1-66a14e976d08.jpg?v=1730296165","url":"https:\/\/surprise-castle.myshopify.com\/products\/logic-design-and-verification-using-systemverilog-revised-9781523364022","provider":"Surprise Castle","version":"1.0","type":"link"}