{"product_id":"llvm-compiler-for-risc-v-architecture-a-unique-approach-to-vectorization-9798868821684","title":"LLVM Compiler for Risc-V Architecture: A Unique Approach to Vectorization","description":"\u003cp\u003eThis book offers a comprehensive introduction to the RISC-V RVV extension and its integration with LLVM-based compilers. It covers the LLVM VPlan-based Loop Vectorizer and SLP Vectorizer, along with additional insights into the clang frontend, OpenMP support, and RVV-specific clang directives provided by SiFive.\u003c\/p\u003e \u003cp\u003eGiven the limited information currently available on RVV and its support in modern compilers, this book fills a crucial gap. RVV introduces a unique approach to vectorization--Vector Length Agnostic (VLA) vectorization--which stands out from the fixed vectors of x86 and the runtime-defined, yet fixed, ARM-based SVE and SVE2 extensions.\u003c\/p\u003e \u003cp\u003eReaders will gain an understanding of RVV-specific VLA-based vectorization support in LLVM-based compilers, which are still under development. The book also provides early insights into the ongoing support for RVV in LLVM.\u003c\/p\u003e \u003cp\u003e\u003cstrong\u003eWhat You'll Learn\u003c\/strong\u003e\u003c\/p\u003e \u003cul\u003e \u003cli\u003eGain foundational knowledge of RISC-V and the RVV extension.\u003c\/li\u003e \u003cli\u003eLearn design and implementation of LLVM vectorizers.\u003c\/li\u003e \u003cli\u003eLearn to optimize performance with RVV-specific clang directives.\u003c\/li\u003e \u003cli\u003eExplore the unique Vector Length Agnostic (VLA) vectorization.\u003c\/li\u003e \u003cli\u003eDiscover the differences between RVV and other vector extensions.\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003cstrong\u003eWho This Book Is For\u003c\/strong\u003e\u003c\/p\u003e \u003cp\u003e1. For the engineers, who would like to get more info about RISC-V in general and RISC-V Vectorextension particularly.\u003c\/p\u003e \u003cp\u003e2. For the developers, trying to get the performance using RVV.\u003c\/p\u003e \u003cp\u003e3. For LLVM compiler developers, trying or learn more about vectorization support in LLVM.4.\u003c\/p\u003e \u003cp\u003e4. For the students, who learn new about RISC- V, its extensions, interested in compiler development.\u003c\/p\u003e \u003cp\u003e \u003c\/p\u003e\u003cbr\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eAbout the Author\u003c\/b\u003e\u003cbr\u003e\u003cp\u003eAlexey Bataev is an experienced compiler engineer with a proven track record in software systems development, specializing in compilers, embedded platforms, and toolchain infrastructure. Areas of expertise include C++, LLVM, Clang, SLP Vectorization, OpenMP, Embedded Linux, and test automation. Holds a Ph.D. in Computer Science. Maintainer of the SLP Vectorizer in LLVM, OpenMP support in Clang. Author of peer-reviewed publications in the field of compiler technology.\u003c\/p\u003e\u003cbr\u003e","brand":"Apress","offers":[{"title":"Default Title","offer_id":52034093646098,"sku":"9798868821684","price":54.99,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0831\/4771\/8930\/files\/img_2617879f-78e7-48fc-93fa-edc5c3b7fe1f.jpg?v=1770985980","url":"https:\/\/surprise-castle.myshopify.com\/products\/llvm-compiler-for-risc-v-architecture-a-unique-approach-to-vectorization-9798868821684","provider":"Surprise Castle","version":"1.0","type":"link"}